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Data Sheet, Rev. 1.0, Mar. 2004
HYS72D32300GBR-[5/6]-C HYS72D64300GBR-[5/6]-C HYS72D64320GBR-[5/6]-C HYS72D128320GBR-6-C
184-Pin Registered Double Data Rate SDRAM Module Reg DIMM DDR SDRAM
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Edition 2004-03 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany (c) Infineon Technologies AG 2004. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data Sheet, Rev. 1.0, Mar. 2004
HYS72D32300GBR-[5/6]-C HYS72D64300GBR-[5/6]-C HYS72D64320GBR-[5/6]-C HYS72D128320GBR-6-C
184-Pin Registered Double Data Rate SDRAM Module Reg DIMM DDR SDRAM
Memory Products
Never
stop
thinking.
HYS72D32300GBR-[5/6]-C HYS72D64300GBR-[5/6]-C HYS72D64320GBR-[5/6]-C HYS72D128320GBR- 6-CHYS72D64300GBR-[5/6]-C HYS72D64320GBR-[5/6]-C Revision History: Previous Version: Page 20,21 8,22 24,27 Rev. 1.0 Rev. 0.5 2004-03
Subjects (major changes since last revision)
Idd values updated
editorial changes Changed SPD Code Byte 99 - 127 to FF
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
Template: mp_a4_v2.2_2003-10-07.fm
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Table of Contents 1 1.1 1.2 2 3 3.1 4 4.1 5 6 7 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Application Note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Data Sheet
5
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Overview
1
1.1
* * * * * * * * * * * *
Overview
Features
184-Pin Registered 8-Byte Dual-In-Line DDR SDRAM Module for "1U" PC, Workstation and Server main memory applications One rank 32 M x 72 and 64M x 72 and two ranks 64 M x72 and 128 M x72 organization JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) with a single + 2.5 V ( 0.2 V) power supply and + 2.6 V ( 0.1 V) power supply for DDR400 Built with 256-Mbit DDR SDRAMs in P-TFBGA-60-1 packages Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) Auto Refresh (CBR) and Self Refresh All inputs and outputs SSTL_2 compatible Re-drive for all input signals using register and PLL devices. Serial Presence Detect with E2PROM Low Profile Modules form factor: 133.35 mm x 28.58 mm x 4.00 mm / 2.64 mm and for 1GB 133.35 mm x 30.48 mm (1.2")x 4.00 mm JEDEC standard reference layout for one rank 256 MB, 512 MB and two ranks 512 MB, 1 GB: PC2700 and PC3200 Registered DIMM Raw Cards A,B,C,D Gold plated contacts Performance -5 Component Module @CL3 @CL2.5 @CL2 DDR400B PC3200-3033 -6 DDR333B PC2700-2533 166 166 133 Unit -- -- MHz MHz MHz
Table 1
Part Number Speed Code Speed Grade max. Clock Frequency
fCK3 fCK2.5 fCK2
200 166 133
1.2
Description
The HYS72D[128/64/32][300/320]GBR-[5/6]-C and HYS72D64320GBR-5-C are low profile versions of the standard Registered DIMM modules suitable for 1U Server Applications. The Low Profile DIMM versions are available as 32 M x72 (256 MB), 64 M x72 (512 MB) and 128 M x72 (1 GB) The memory array is designed with Double Data Rate Synchronous DRAMs for ECC applications. All control and address signals are re-driven on the DIMM using register devices and a PLL for the clock distribution. This reduces capacitive loading to the system bus, but adds one cycle to the SDRAM timing. A variety of decoupling capacitors are mounted on the PC board. The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
Data Sheet
6
Rev. 1.0, 2004-03 07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Overview
Table 2 Type
Ordering Information Compliance Code Description SDRAM Technology
PC3200 (CL = 3.0) HYS72D32300GBR-5-C HYS72D64300GBR-5-C HYS72D64320GBR-5-C PC3200R-30330-A0 1 Rank 256 MB Registered DIMM ECC PC3200R-30330-C0 1 Rank 512 MB Registered DIMM ECC PC3200R-30330-B0 2 Ranks 512 MB Registered DIMM ECC 256 Mbit (x8) 256 Mbit (x4) 256 Mbit (x8)
PC2700 (CL = 2.5, tRP = tRCD = 3 at tCK = 6ns) HYS72D32300GBR-6-C HYS72D64300GBR-6-C HYS72D64320GBR-6-C PC2700R-25330-A0 1 Rank 256 MB Registered DIMM ECC PC2700R-25330-C0 1 Rank 512 MB Registered DIMM ECC PC2700R-25330-B0 2 Ranks 512 MB Registered DIMM ECC 256 Mbit (x8) 256 Mbit (x4) 256 Mbit (x8) 256 Mbit (x4)
HYS72D128320GBR-6-C PC2700R-25330-D0 2 Ranks 1 GB Registered DIMM ECC
Data Sheet
7
Rev. 1.0, 2004-03 07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Pin Configuration
2
Pin Configuration
Table 3 Pin# Name 125 29 122 27 141 118 115 A6 A7 A8 A9 A10 AP I I I I NC I I NC I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL - SSTL SSTL SSTL Clock Signal Complement Clock Clock Enable Rank 0 Clock Enable Rank 1 Note: 2-rank module NC Note: 1-rank module Chip Select of Rank 0 Chip Select of Rank 1 Note: 2-ranks module NC Note: 1-rank module Row Address Strobe Column Address Strobe Write Enable NC NC - 167 NC A13 NC I - SSTL A11 A12 Pin Configuration of RDIMM (cont'd) Pin Buffer Function Type Type I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Address Signal 12 Note: Module based on 256 Mbit or larger dies Note: 128 Mbit module Note: 1 Gbit module based Address Bus 11:0
The pin configuration of the Registered DDR SDRAM DIMM is listed by function in Table 3 (184 pins). The abbreviations used in columns Pin and Buffer Type are explained in Table 4 and Table 5 respectively. The pin numbering is depicted in Figure 1. Table 3 Pin# Name Clock Signals 137 138 21 111 CK0 CK0 CKE0 CKE1 Pin Configuration of RDIMM Pin Buffer Function Type Type
Control Signals 157 158 S0 S1
Address Signal 13 based
154 65 63 10
RAS CAS WE
Note: Module based on 512 Mbit or smaller dies
RESET I
LVRegister Reset CMOS Forces registered inputs low Note: For detailed description of the Power Up and Power Management see the Application Note at the end of data sheet
Address Signals 59 52 48 43 41 130 37 32 BA0 BA1 A0 A1 A2 A3 A4 A5 I I I I I I I I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Address Bus 11:0 Bank Address Bus 1:0 Address Bus 11:0
Data Sheet
8
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Pin Configuration Table 3 Pin# Name Data Signals 2 4 6 8 94 95 98 99 12 13 19 20 105 106 109 110 23 24 28 31 114 117 121 123 33 35 39 40 126 127 131 133 53 55 57 60 146 147 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Bus 63:0 Pin Configuration of RDIMM (cont'd) Pin Buffer Function Type Type Table 3 Pin# Name 150 151 61 64 68 69 153 155 161 162 72 73 79 80 165 166 170 171 83 84 87 88 174 175 178 179 44 45 49 51 134 135 142 144 5 14 25 36 56 67 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 Pin Configuration of RDIMM (cont'd) Pin Buffer Function Type Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Strobes 8:0 Note: See block diagram for corresponding DQ signals Check Bits 7:0 Data Bus 63:0
Data Sheet
9
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Pin Configuration Table 3 Pin# Name 78 86 47 97 DQS6 DQS7 DQS8 DM0 DQS9 107 DM1 Pin Configuration of RDIMM (cont'd) Pin Buffer Function Type Type I/O I/O I/O I I/O I SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL Data Mask 0 Note: x8 based module Data Strobe 9 Note: x4 based module Data Mask 1 Note: x8 based module DQS10 I/O 119 DM2 I Data Strobe 10 Note: x4 based module Data Mask 2 Note: x8 based module DQS11 I/O 129 DM3 I Data Strobe 11 Note: x4 based module Data Mask 3 Note: x8 based module DQS12 I/O 149 DM4 I Data Strobe 12 Note: x4 based module Data Mask 4 Note: x8 based module DQS13 I/O 159 DM5 I Data Strobe 13 Note: x4 based module Data Mask 5 Note: x8 based module DQS14 I/O 169 DM6 I Data Strobe 14 Note: x4 based module Data Mask 6 Note: x8 based module DQS15 I/O 177 DM7 I Data Strobe 15 Note: x4 based module Data Mask 7 Note: x8 based module DQS16 I/O 140 DM8 I Data Strobe 16 Note: x4 based module Data Mask 8 Note: x8 based module DQS17 I/O Data Strobe 17 Note: x4 based module 15, VDDQ 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 PWR - Data Strobes 8:0 Table 3 Pin# Name EEPROM 92 91 181 182 183 1 184 SCL SDA SA0 SA1 SA2 I I/O I I I CMOS Serial Bus Clock OD Serial Bus Data CMOS Slave Address Select CMOS Bus 2:0 CMOS I/O Reference Voltage EEPROM Power Supply I/O Driver Power Supply Pin Configuration of RDIMM (cont'd) Pin Buffer Function Type Type
Power Supplies
VREF AI - VDDSPD PWR -
VDD 7, 38, 46, 70, 85, 108, 120, 148, 168
PWR -
Power Supply
Data Sheet
10
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Pin Configuration Table 3 Pin# Name Pin Configuration of RDIMM (cont'd) Pin Buffer Function Type Type GND - Ground Plane
Table 4 I O I/O AI PWR GND NU NC
Abbreviations for Pin Type Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Usable (JEDEC Standard) Not Connected (JEDEC Standard)
Abbreviation Description
VSS 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176
Other Pins 82
Table 5 SSTL LV-CMOS
Abbreviations for Buffer Type Serial Stub Terminalted Logic (SSTL2) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
Abbreviation Description
CMOS
OD
VDDID
O
OD
VDD Identification
Note: Pin in tristate, indicating VDD and VDDQ nets connected on PCB
NC 9, 16, 17, 71, 75, 76, 90, 101, 102, 103, 113, 163, 173
NC
-
Not connected Pins not connected on Infineon RDIMM's
Data Sheet
11
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Pin Configuration
VREF DQS0 NC DQ09 NC CKE0 DQS2 A7 DQ24 A4 -
Pin 001 Pin 005 Pin 009 Pin 013 Pin 017 Pin 021 Pin 025 Pin 029 Pin 033 Pin 037
VSS VDD VSS VDDQ DQ10 DQ16 A9 DQ19 DQ25 DQ26 -
Pin 003 Pin 007 Pin 011 Pin 015 Pin 019 Pin 023 Pin 027 Pin 031 Pin 035 Pin 039
Pin 004 Pin 008 Pin 012 Pin 016 Pin 020 Pin 024 Pin 028 Pin 032 Pin 036 Pin 040
- DQ01 - DQ03 - DQ08 - NC - DQ11 - DQ17 - DQ18 - A5 - DQS3 - DQ27
Pin 002 Pin 006 Pin 010 Pin 014 Pin 018 Pin 022 Pin 026 Pin 030 Pin 034 Pin 038 -
DQ00 DQ02 RESET DQS1 VSS VDDQ VSS VDDQ VSS VDD
A2 CB01 CB02 DQ32 DQ34 DQ40 CAS DQ43 DQ49 VDDQ VSS VDD VSS VSS DM00/DQS9 NC DQ12 DQ14 NC DQ21 DQ22 A6 DM3/DQS12 DQ31 CK0 A10/AP VSS DM4/DQS13 DQ44 S0 DQ46 DQ52 DM6/DQS15 NC DM7/DQS16 SA0 -
Pin 041 Pin 045 Pin 049 Pin 053 Pin 057 Pin 061 Pin 065 Pin 069 Pin 073 Pin 077 Pin 081 Pin 085 Pin 089 Pin 093 Pin 097 Pin 101 Pin 105 Pin 109 Pin 113 Pin 117 Pin 121 Pin 125 Pin 129 Pin 133 Pin 137 Pin 141 Pin 145 Pin 149 Pin 153 Pin 157 Pin 161 Pin 165 Pin 169 Pin 173 Pin 177 Pin 181
A1 DQS8 CB03 DQ33 BA0 WE DQS5 NC NC DQ50 DQ56 DQ58 SDA DQ05 DQ07 NC DM1/DQS10 CKE1/NC A12/NC DM2/DQS11 DQ23 DQ29 DQ30 CB5 VSS VDDQ DQ37 DQ39 DQ45 DM5/DQS14 NC A13/NC DQ55 DQ61 DQ63 SA2 -
Pin 043 Pin 047 Pin 051 Pin 055 Pin 059 Pin 063 Pin 067 Pin 071 Pin 075 Pin 079 Pin 083 Pin 087 Pin 091 Pin 095 Pin 099 Pin 103 Pin 107 Pin 111 Pin 115 Pin 119 Pin 123 Pin 127 Pin 131 Pin 135 Pin 139 Pin 143 Pin 147 Pin 151 Pin 155 Pin 159 Pin 163 Pin 167 Pin 171 Pin 175 Pin 179 Pin 183
Pin 044 Pin 048 Pin 052 Pin 056 Pin 060 Pin 064 Pin 068 Pin 072 Pin 076 Pin 080 Pin 084 Pin 088 Pin 092 Pin 096 Pin 100 Pin 104 Pin 108 Pin 112 Pin 116 Pin 120 Pin 124 Pin 128 Pin 132 Pin 136 Pin 140 Pin 144 Pin 148 Pin 152 Pin 156 Pin 160 Pin 164 Pin 168 Pin 172 Pin 176 Pin 180 Pin 184 -
CB00 A0 BA1 DQS4 DQ35 DQ41 DQ42 DQ48 NC DQ51 DQ57 DQ59 SCL VDDQ VSS VDDQ VDD VDDQ VSS VDD VSS VDDQ VSS VDDQ DM8/DQS17 CB07 VDD VSS VDDQ VSS VDDQ VDD VDDQ VSS VDDQ VDDSPD
Pin 042 Pin 046 Pin 050 Pin 054 Pin 058 Pin 062 Pin 066 Pin 070 Pin 074 Pin 078 Pin 082 Pin 086 Pin 090 Pin 094 Pin 098 Pin 102 Pin 106 Pin 110 Pin 114 Pin 118 Pin 122 Pin 126 Pin 130 Pin 134 Pin 138 Pin 142 Pin 146 Pin 150 Pin 154 Pin 158 Pin 162 Pin 166 Pin 170 Pin 174 Pin 178 Pin 182 -
FRONTSIDE
BACKSIDE
VSS VDD VSS VDDQ VSS VDDQ VSS VDD VSS DQS6 VDDID DQS7 NC DQ04 DQ06 NC DQ13 DQ15 DQ20 A11 A8 DQ28 A3 DQ04 CK0 CB06 DQ36 DQ38 RAS S1 /NC DQ47 DQ53 DQ54 DQ60 DQ62 SA1
MPPD0020
Figure 1 Table 6
Pin Configuration 184 Pins, Reg Address Table Memory SDRAMs # of SDRAMs # of row/rank/ Refresh Ranks columns bits 1 1 32 M x8 64 M x4 9 18 13 / 2 / 10 13 / 2 / 11 8K 8K Period Interval
Density Organization
256 MB 512 MB
32 M x72 64 M x72
64 ms 64 ms
7.8 s 7.8 s
Data Sheet
12
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Pin Configuration Table 6 Address Table Memory SDRAMs # of SDRAMs # of row/rank/ Refresh Ranks columns bits 2 2 32 M x8 64 M x4 18 36 13 / 2 / 10 13 / 2 / 11 8K 8K Period Interval
Density Organization
512 MB 1 GB
64 M x72 128 M x72
64 ms 64 ms
7.8 s 7.8 s
CK0 CK0 S0 CKE0 BA0 - BA1 A0 - An RAS CAS WE PCK PCK RESET S0 DM0/DQS9 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM1/DQS10 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM2/DQS11 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 SCL SAD SA0 SA1 SA2 VSS
PLL R E G I S T E R
PCK PCK RS0 RCKE0 RBA0 - RBA1 RA0-RAn RRAS RCAS RWE
CS: SDRAMs D0- D8 CKE: SDRAMs D0 - D8 BA0 - BA1: SDRAMs D0 - D8 A0 - An: SDRAMs D0 - D8 RAS: SDRAMs D0 - D8 CAS: SDRAMs D0 - D8 WE: SDRAMs D0 - D8
DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 SCL SAD A0 A1 A2 WP
D0
DM3/DQS12 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM4/DQS13 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM5/DQS14 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 VDD,SPD VDD/VDDQ VREF VSS VDDID
DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D3
DM6/DQS15 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM7/DQS16 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM8/DQS17 DQS8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7
DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM CS DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
D6
D1
D4
D7
D2
D5
D8
E0
VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D8 VREF: SDRAMs D0 - D8 VSS: SDRAMs D0 - D8 Strap: see Note 1
MPBD1101
Figure 2 Notes
Block Diagram Raw Card A x72 1 Rank x8, ECC 3. BAn, An, RAS, CAS, WE resistors are 22 ohms 5%
1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 ohms 5% Data Sheet 13
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Pin Configuration
CK0 CK0 S0 CKE0 S1 CKE1 BA0 - BA1 A0 - An RAS CAS WE PCK PCK RESET S0 S1 DM0/DQS9 DQS0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM1/DQS10 DQS1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DM2/DQS11 DQS2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM3/DQS12 DQS3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VDD,SPD VDD/VDDQ VREF VSS VDDID
PLL R E G I S T E R
PCK PCK RS0 RCKE0 RS1 RCKE1 RBA0 - RBA1 RA0 - RAn RRAS RCAS RWE
CKE: SDRAMs D0 - D8 CKE: SDRAMs D9 - D17 BA0 - BA1: SDRAMs D0 - D17 A0 - An: SDRAMs D0 - D17 RAS: SDRAMs D0 - D17 CAS: SDRAMs D0 - D17 WE: SDRAMs D0 - D17
SCL SAD SA0 SA1 SA2 VSS
SCL SAD A0 A1 A2 WP
E0
DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
D0 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D1 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D2 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D3 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
D9 DM4/DQS13 DQS4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D10 DM5/DQS14 DQS5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D11 DM6/DQS15 DQS6 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D12 DM7/DQS16 DQS7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM8/DQS17 DQS8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
D4 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D5 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D7 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D8 DM DQS I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
CS
D13
CS
CS
CS
CS
D14
CS
CS
CS
CS
D15
CS
CS
CS
CS
D16
CS
CS
D17
VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D17 VREF: SDRAMs D0 - D17 VSS: SDRAMs D0 - D17 DM: SDRAMs D0 - D17 Strap: see Note 1
MPBD1401
Figure 3 Notes
Block Diagram Raw Card B x72, 2Ranks x8, ECC 3. BAn, An, RAS, CAS, WE resistors are 22 ohms 5% 4. For Wire per Clock Loading please see Figure: "Diferential Clock Net Wiring"
1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 ohms 5%
Data Sheet
14
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Pin Configuration
CK0 CK0 S0 CKE0 BA0 - BA1 A0 - An RAS CAS WE PCK PCK RESET RS0 DQS0 DQ0 DQ1 DQ2 DQ3 DQS1 DQ8 DQ9 DQ10 DQ11 DQS2 DQ16 DQ17 DQ18 DQ19 DQS3 DQ24 DQ25 DQ26 DQ27 DQS4 DQ32 DQ33 DQ34 DQ35 DQS5 DQ40 DQ41 DQ42 DQ43 VDD,SPD VDD/VDDQ VREF VSS VDDID
PLL R E G I S T E R
PCK PCK RS0 RCKE0 RBA0 - RBA1 RA0 - RAn RRAS RCAS RWE
CS: SDRAMs D0- D17 CKE: SDRAMs D0 - D17 BA0 - BA1: SDRAMs D0 - D17 A0 - An: SDRAMs D0 - D17 RAS: SDRAMs D0 - D17 CAS: SDRAMs D0 - D17 WE: SDRAMs D0 - D17
DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
D0 DQS6 DQ48 DQ49 DQ50 DQ51 D1 DQS7 DQ56 DQ57 DQ58 DQ59 D2 DQS8 CB0 CB1 CB2 CB3 D3 DQS9 DQ4 DQ5 DQ6 DQ7 D4 DQS10 DQ12 DQ13 DQ14 DQ15 D5 DQS11 DQ20 DQ21 DQ22 DQ23 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
D6 DQS12 DQ28 DQ29 DQ30 DQ31 D7 DQS13 DQ36 DQ37 DQ38 DQ39 D8 DQS14 DQ44 DQ45 DQ46 DQ47 D9 DQS15 DQ52 DQ53 DQ54 DQ55 D10 DQS16 DQ60 DQ61 DQ62 DQ63 D11 DQS17 CB4 CB5 CB6 CB7 SCL SAD SA0 SA1 SA2 VSS DQS I/O 0 I/O 1 I/O 2 I/O 3 SCL SAD A0 A1 A2 WP DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3 DQS I/O 0 I/O 1 I/O 2 I/O 3
CS
D12
CS
CS
CS
D13
CS
CS
CS
D14
CS
CS
CS
D15
CS
CS
CS
D16
CS
CS
CS
D17
VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D17 VREF: SDRAMs D0 - D17 VSS: SDRAMs D0 - D17 Strap: see Note 1
E0
MPBD1501
Figure 4 Notes
Block Diagram Raw Card C x72 1 Rank x4, ECC 3. BAn, An, RAS, CAS, WE resistors are 22 ohms 5%
1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 22 ohms 5%
Data Sheet
15
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Pin Configuration
CK0 CK0 S0 CKE0 S1 CKE1 BA0 - BA1 A0 - An RAS CAS WE PCK PCK RESET RS0 RCKE0 RS1 RCKE1 DQS0 DQ0 DQ1 DQ2 DQ3 DQS1 DQ8 DQ9 DQ10 DQ11 DQS10 DQ12 DQ13 DQ14 DQ15 DQS9 DQ4 DQ5 DQ6 DQ7 DQS11 DQ20 DQ21 DQ22 DQ23 DQS2 DQ16 DQ17 DQ18 DQ19 DQS3 DQ24 DQ25 DQ26 DQ27 DQS17 CB4 CB5 CB6 CB7 DQS12 DQ28 DQ29 DQ30 DQ31
PLL R E G I S T E R
PCK PCK RS0 RCKE0 RS1 RCKE1 RBA0 - RBA1 RA0-RAn RRAS RCAS RWE
BA0 - BA1: SDRAMs D0 - D35 A0 - An: SDRAMs D0 - D35 RAS: SDRAMs D0 - D35 CAS: SDRAMs D0 - D35 WE: SDRAMs D0 - D35
VDD,SPD VDD/VDDQ VREF VSS VDDID Strap: see Note 1 SCL SAD SA0 SA1 SA2 VSS
VDD: SPD EEPROM E0 VDD/VDDQ: SDRAMs D0 - D35 VREF: SDRAMs D0 - D35 VSS: SDRAMs D0 - D35 DM: SDRAMs D0 - D35 SCL SAD A0 A1 A2 WP E0
CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3
D4
CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3
D6 DQS7 DQ56 DQ57 DQ58 DQ59 D2 DQS6 DQ48 DQ49 DQ50 DQ51 D14 DQS15 DQ52 DQ53 DQ54 DQ55 D10 DQS16 DQ60 DQ61 DQ62 DQ63 D22 DQS14 DQ44 DQ45 DQ46 DQ47 D18 DQS5 DQ40 DQ41 DQ42 DQ43 D26 DQS4 DQ32 DQ33 DQ34 DQ35 D30 DQS8 CB0 CB1 CB2 CB3 D34 DQS13 DQ36 DQ37 DQ38 DQ39
CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3
D5
CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3 CKE CS DQS I/O 0 I/O 1 I/O 2 I/O 3
D7
D0
D1
D3
D12
D13
D15
D8
D9
D11
D20
D21
D23
D16
D17
D19
D24
D25
D27
D28
D28
D31
D32
D33
D35
MPBD1061
Figure 5 Notes
Block Diagram Raw Card D x72 2 Ranks x4, ECC 3. BAn, An, RAS, CAS, WE resistors are 22 ohms 5% 4. For Wire per Clock Loading please see Figure "Differental Clock Net Wiring"
1. VDD = VDDQ, therefore VDDID strap open 2. DQ, DQS, DM resistors are 18 ohms 5%
Data Sheet
16
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Electrical Characteristics
3
3.1
Table 7 Parameter
Electrical Characteristics
Operating Conditions
Absolute Maximum Ratings Symbol min. Values typ. - - - - - - 1 50 max. -0.5 -1 -1 -1 0 -55 - - Unit Note/ Test Condition V V V V C C W mA - - - - - - - -
Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient) Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
VIN, VOUT VIN VDD VDDQ TA TSTG PD IOUT
VDDQ +0.5
+3.6 +3.6 +3.6 +70 +150 - -
Attention: Permanent damage to the device may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only, and functional operation should be restricted to recommended operation conditions. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability and exceeding only one of the values may cause irreversible damage to the integrated circuit. Table 8 Parameter Device Supply Voltage Device Supply Voltage Electrical Characteristics and DC Operating Conditions Symbol Min. Values Typ. 2.5 2.6 2.5 2.6 2.5 Max. 2.7 2.7 2.7 2.7 3.6 0 V V V V V V 2.3 2.5 2.3 2.5 2.3 0 Unit Note/Test Condition 1)
VDD
VDD Output Supply Voltage VDDQ Output Supply Voltage VDDQ EEPROM supply voltage VDDSPD Supply Voltage, I/O Supply VSS, Voltage VSSQ VREF Input Reference Voltage I/O Termination Voltage VTT
(System) Input High (Logic1) Voltage VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and CK Inputs Input Differential Voltage, CK and CK Inputs VI-Matching Pull-up Current to Pull-down Current
fCK 166 MHz fCK > 166 MHz 2) fCK 166 MHz 3) fCK > 166 MHz 2)3)
-- --
4) 5)
0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V
VREF - 0.04 VREF + 0.15
-0.3 -0.3 0.36 0.71
VREF + 0.04 V VDDQ + 0.3 V VREF - 0.15 V VDDQ + 0.3 V VDDQ + 0.6
1.4 V --
8) 8) 8)
VIN(DC) VID(DC)
VIRatio
8)6)
7)
Data Sheet
17
Rev. 1.0, 2004-03 07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Electrical Characteristics Table 8 Parameter Input Leakage Current Electrical Characteristics and DC Operating Conditions (cont'd) Symbol Min. Values Typ. Max. 2 A Any input 0 V VIN VDD; All other pins not under test = 0 V 8)9) DQs are disabled; 0 V VOUT VDDQ -2 Unit Note/Test Condition 1)
II
Output Leakage Current Output High Current, Normal Strength Driver Output Low Current, Normal Strength Driver
1) 0 C TA 70 C
IOZ IOH IOL
-5 -- 16.2
5 -16.2 --
A mA mA
VOUT = 1.95 V VOUT = 0.35 V
2) DDR400 conditions apply for all clock frequencies above 166 MHz 3) Under all conditions, VDDQ must be less than or equal to VDD. 4) Peak to peak AC noise on VREF may not exceed 2% VREF (DC). VREF is also expected to track noise variations in VDDQ. 5) VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 6) VID is the magnitude of the difference between the input level on CK and the input level on CK. 7) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. 8) Inputs are not recognized as valid until VREF stabilizes. 9) Values are shown per DDR SDRAM component
Data Sheet
18
Rev. 1.0, 2004-03 07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Current Specification and Conditions
4
Table 9 Parameter
Current Specification and Conditions
IDD Conditions
Symbol
Operating Current 0 one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current 1 one bank; active/read/precharge; Burst Length = 4; see component data sheet. Precharge Power-Down Standby Current all banks idle; power-down mode; CKE VIL,MAX Precharge Floating Standby Current CS VIH,,MIN, all banks idle; CKE VIH,MIN; address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current CS VIHMIN, all banks idle; CKE VIH,MIN; VIN = VREF for DQ, DQS and DM; address and other control inputs stable at VIH,MIN or VIL,MAX. Active Power-Down Standby Current one bank active; power-down mode; CKE VILMAX; VIN = VREF for DQ, DQS and DM. Active Standby Current one bank active; CS VIH,MIN; CKE VIH,MIN; tRC = tRAS,MAX; DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current Read one bank active; Burst Length = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT = 0 mA Operating Current Write one bank active; Burst Length = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B Auto-Refresh Current tRC = tRFCMIN, burst refresh Self-Refresh Current CKE 0.2 V; external clock on Operating Current 7 four bank interleaving with Burst Length = 4; see component data sheet.
IDD0
IDD1 IDD2P IDD2F
IDD2Q
IDD3P IDD3N
IDD4R
IDD4W
IDD5 IDD6 IDD7
Data Sheet
19
Rev. 1.0, 2004-03 07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Current Specification and Conditions
Table 10
IDD Specification for PC3200
HYS72D32300GBR-5-C HYS72D64300GBR-5-C HYS72D64320GBR-5-C Unit Note/ Test Conditions1) 2)
Part Number & Organization
256 MB x72 1 Rank -5 Typ. 1510 1600 680 914 824 761 986 1645 1690 2140 657 2770 Max. 1690 1780 689 968 896 806 1049 1780 1825 2590 670 3130
512 MB x72 1 Rank -5 Typ. 2140 2320 716 1184 1004 878 1328 2410 2500 3400 669 4660 Max. 2500 2680 734 1292 1148 968 1454 2680 2770 4300 694 5380
512 MB x72 2 Ranks -5 Typ. 1852 1942 788 1184 1004 878 1328 1987 2032 2482 669 3112 Max. 2095 2185 824 1292 1148 968 1454 2185 2230 2995 694 3535 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 2) Module IDD is calculated on the basis of component IDD and includes Register an PLL 3) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for single two bank modules (n: number of components per module bank)
Data Sheet
20
Rev. 1.0, 2004-03 07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Current Specification and Conditions
Table 11
IDD Specification for PC2700
HYS72D128320GBR-6-C HYS72D32300GBR-6-C HYS72D64300GBR-6-C HYS72D64320GBR-6-C Unit Note/ Test Conditions1) 2)
Part Number & Organization
256 MB x72 1 Rank -6 Typ. 1270 1360 466 655 583 529 718 1360 1405 1810 443 2350 Max. 1405 1495 475 700 646 565 772 1495 1540 2170 455 2665
512 MB x72 1 Rank -6 Typ. 1810 1990 502 880 736 628 1006 1990 2080 2890 455 3970 Max. 2080 2260 520 970 862 700 1114 2260 2350 3610 480 4600
512 MB x72 2 Ranks -6 Typ. 1558 1648 574 880 736 628 1006 1648 1693 2098 455 2638 Max. 1747 1837 610 970 862 700 1114 1837 1882 2512 480 3007
1 GB x72 2 Ranks -6 Typ. 2386 2566 718 1330 1042 826 1582 2566 2656 3466 480 4546 Max. 2764 2944 790 1510 1294 970 1798 2944 3034 4294 531 5284 mA mA mA mA mA mA mA mA mA mA mA mA
3) 3)4) 5) 5) 5) 5) 5) 3)4) 3) 3) 5) 3)4)
Symbol
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
1) Test condition for maximum values: VDD = 2.7 V, TA = 10 C 2) Module IDD is calculated on the basis of component IDD and includes Register an PLL 3) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) n * IDDx[component] + n * IDD3N[component] for two bank modules (n: number of components per module bank) 4) DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently depending on load conditions 5) The module IDD values are calculated from the component IDD datasheet values are: n * IDDx[component] for single bank modules (n: number of components per module bank) 2 * n * IDDx[component] for single two bank modules (n: number of components per module bank)
Data Sheet
21
Rev. 1.0, 2004-03 07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Current Specification and Conditions
4.1
Table 12 Parameter
AC Characteristics
AC Timing - Absolute Specifications for PC3200 and PC2700 Symbol -5 DDR400B Min. Max. +0.5 +0.6 0.55 0.55 8 12 12 -- -- -- -- +0.7 +0.7 1.25 +0.40 +0.50 -- -- -- -- -- 0.60 -- -- -- -- -- -6 DDR333 Min. -0.7 -0.6 0.45 0.45 6 6 7.5 0.45 0.45 2.2 1.75 -0.7 -0.7 0.75 -- -- 0.35 0.2 0.2 2 0 0.40 0.25 0.75 0.8 0.75 0.8 Max. +0.7 +0.6 0.55 0.55 12 12 12 -- -- -- -- +0.7 +0.7 1.25 +0.40 +0.50 -- -- -- -- -- 0.60 -- -- -- -- -- ns ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
Unit Note/ Test Condition 1)
DQ output access time from CK/CK DQS output access time from CK/CK CK high-level width CK low-level width Clock Half Period Clock cycle time
tAC tDQSCK tCH tCL tHP tCK
-0.5 -0.6 0.45 0.45 5 6 7.5
tCK tCK
ns ns ns ns ns ns ns ns ns ns
min. (tCL, tCH)
min. (tCL, tCH)
CL = 3.0
2)3)4)5)
CL = 2.5
2)3)4)5)
CL = 2.0
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)6)
DQ and DM input hold time DQ and DM input setup time Control and Addr. input pulse width (each input) DQ and DM input pulse width (each input) Data-out high-impedance time from CK/CK Data-out low-impedance time from CK/CK Write command to 1st DQS latching transition DQS-DQ skew (DQS and associated DQ signals) Data hold skew factor
tDH tDS tIPW tDIPW tHZ tLZ tDQSS tDQSQ
0.4 0.4 2.2 1.75 -- -0.7 0.72 -- --
2)3)4)5)6) 2)3)4)5)7) 2)3)4)5)7) 2)3)4)5)
tCK
ns ns ns
TFBGA 2)3)4)5) TFBGA 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tQHS DQ/DQS output hold time tQH DQS input low (high) pulse width (write cycle) tDQSL,H DQS falling edge to CK setup time (write cycle) tDSS DQS falling edge hold time from CK (write tDSH
cycle) Mode register set command cycle time Write preamble setup time Write postamble Write preamble Address and control input setup time
tHP -tQHS
0.35 0.2 0.2 2 0 0.40 0.25 0.6 0.7
tCK tCK tCK tCK
ns
tMRD tWPRES tWPST tWPRE tIS
2)3)4)5) 2)3)4)5)8) 2)3)4)5)9) 2)3)4)5)
tCK tCK
ns ns ns ns
fast slew rate
3)4)5)6)10)
slow slew rate3)4)5)6)10) fast slew rate
3)4)5)6)10)
Address and control input hold time
tIH
0.6 0.7
slow slew rate3)4)5)6)10)
Data Sheet
22
Rev. 1.0, 2004-03 07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Current Specification and Conditions Table 12 Parameter AC Timing - Absolute Specifications for PC3200 and PC2700 Symbol -5 DDR400B Min. Max. 1.1 0.60 70E+3 -- -- -- -- -- -- -6 DDR333 Min. 0.9 0.40 42 60 72 18 18 12 15 Max. 1.1 0.60 -- -- -- -- -- -- Unit Note/ Test Condition 1)
tRPRE Read postamble tRPST Active to Precharge command tRAS Active to Active/Auto-refresh command period tRC Auto-refresh to Active/Auto-refresh command tRFC
Read preamble period Active to Read or Write delay Precharge command period Active to Autoprecharge delay Active bank A to Active bank B command Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Exit self-refresh to non-read command Exit self-refresh to read command Average Periodic Refresh Interval
0.9 0.40 40 55 70 15 15 10 15
tCK tCK
ns ns ns ns ns ns ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
70E+3 ns
tRCD tRP tRAP tRRD tWR tDAL tWTR tXSNR tXSRD tREFI
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)11)
tRCD or tRASmin
(tWR/tCK)+(tRP/tCK) 2 75 200 -- -- -- -- 7.8 1 75 200 -- -- -- -- 7.8
tCK tCK
ns
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)12)
tCK
s
1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400) 2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) These parameters guarantee device timing, but they are not necessarily tested on each device. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 10) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
23
Rev. 1.0, 2004-03 07302003-2MI6-FOP1
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
SPD Contents
5
Table 13
SPD Contents
SPD Codes for HYS72D[128/64/32][300/320]GBR-5-C HYS72D64300GBR-5-C HYS72D64320GBR-5-C HYS72D32300GBR-5-C 256 MB x72 1 Rank PC3200R-30331 Rev 1.0 HEX 80 08 07 0D 0A 01 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 26 C1 60 50 75 Rev. 1.0, 2004-03 07302003-2MI6-FOP1
Product Type & Organization
512 MB x72 1 Rank PC3200R-30331 Rev 1.0 HEX 80 08 07 0D 0B 01 48 00 04 50 50 02 82 04 04 01 0E 04 1C 01 02 26 C1 60 50 75
512 MB x72 2 Ranks PC3200R-30331 Rev 1.0 HEX 80 08 07 0D 0A 02 48 00 04 50 50 02 82 08 08 01 0E 04 1C 01 02 26 C1 60 50 75
Label Code Jedec SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns]
Data Sheet
24
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
SPD Contents Table 13 SPD Codes for HYS72D[128/64/32][300/320]GBR-5-C HYS72D64300GBR-5-C HYS72D64320GBR-5-C HYS72D32300GBR-5-C 256 MB x72 1 Rank PC3200R-30331 Rev 1.0 HEX 50 3C 28 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 01 00 10 26 C1 00 xx 37 32 44 33 Rev. 1.0, 2004-03 07302003-2MI6-FOP1
Product Type & Organization
512 MB x72 1 Rank PC3200R-30331 Rev 1.0 HEX 50 3C 28 3C 28 80 60 60 40 40 00 37 41 28 28 50 00 01 00 10 5F C1 00 xx 37 32 44 36
512 MB x72 2 Ranks PC3200R-30331 Rev 1.0 HEX 50 3C 28 3C 28 40 60 60 40 40 00 37 41 28 28 50 00 01 00 10 27 C1 00 xx 37 32 44 36
Label Code Jedec SPD Revision Byte# 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 - 71 72 73 74 75 76 Description tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3 Part Number, Char 4
Data Sheet
25
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
SPD Contents Table 13 SPD Codes for HYS72D[128/64/32][300/320]GBR-5-C HYS72D64300GBR-5-C HYS72D64320GBR-5-C HYS72D32300GBR-5-C 256 MB x72 1 Rank PC3200R-30331 Rev 1.0 HEX 32 33 30 30 47 42 52 35 43 20 20 20 20 20 xx xx xx xx xx FF Rev. 1.0, 2004-03 07302003-2MI6-FOP1
Product Type & Organization
512 MB x72 1 Rank PC3200R-30331 Rev 1.0 HEX 34 33 30 30 47 42 52 35 43 20 20 20 20 20 xx xx xx xx xx FF
512 MB x72 2 Ranks PC3200R-30331 Rev 1.0 HEX 34 33 32 30 47 42 52 35 43 20 20 20 20 20 xx xx xx xx xx FF
Label Code Jedec SPD Revision Byte# 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 99 - 127 Description Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4) Blank
Data Sheet
26
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
SPD Contents Table 14 SPD Codes for HYS72D[128/64/32][300/320]GBR-6-C HYS72D128320GBR-6-C HYS72D64300GBR-6-C HYS72D64320GBR-6-C HYS72D32300GBR-6-C 256 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 80 08 07 0D 0A 01 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 26 C1 75 70 00 Rev. 1.0, 2004-03 07302003-2MI6-FOP1
Product Type & Organization
1 GByte x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 80 08 07 0D 0B 02 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26 C1 75 70 00
512 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 80 08 07 0D 0B 01 48 00 04 60 70 02 82 04 04 01 0E 04 0C 01 02 26 C1 75 70 00
512 MB x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 80 08 07 0D 0A 02 48 00 04 60 70 02 82 08 08 01 0E 04 0C 01 02 26 C1 75 70 00
Label Code Jedec SPD Revision Byte# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Description Programmed SPD Bytes in E2PROM Total number of Bytes in E2PROM Memory Type (DDR = 07h) Number of Row Addresses Number of Column Addresses Number of DIMM Ranks Data Width (LSB) Data Width (MSB) Interface Voltage Levels tCK @ CLmax (Byte 18) [ns] tAC SDRAM @ CLmax (Byte 18) [ns] Error Correction Support Refresh Rate Primary SDRAM Width Error Checking SDRAM Width tCCD [cycles] Burst Length Supported Number of Banks on SDRAM Device CAS Latency CS Latency Write Latency DIMM Attributes Component Attributes tCK @ CLmax -0.5 (Byte 18) [ns] tAC SDRAM @ CLmax -0.5 [ns] tCK @ CLmax -1 (Byte 18) [ns]
Data Sheet
27
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
SPD Contents Table 14 SPD Codes for HYS72D[128/64/32][300/320]GBR-6-C HYS72D128320GBR-6-C HYS72D64300GBR-6-C HYS72D64320GBR-6-C HYS72D32300GBR-6-C 256 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 00 48 30 48 2A 40 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 0F C1 00 xx 37 32 44 Rev. 1.0, 2004-03 07302003-2MI6-FOP1
Product Type & Organization
1 GByte x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 49 C1 00 xx 37 32 44
512 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 00 48 30 48 2A 80 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 48 C1 00 xx 37 32 44
512 MB x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 00 48 30 48 2A 40 75 75 45 45 00 3C 48 30 28 50 00 00 00 00 10 C1 00 xx 37 32 44
Label Code Jedec SPD Revision Byte# 26 27 28 29 30 31 32 33 34 35 36 - 40 41 42 43 44 45 46 47 48 - 61 62 63 64 65 - 71 72 73 74 75 Description tAC SDRAM @ CLmax -1 [ns] tRPmin [ns] tRRDmin [ns] tRCDmin [ns] tRASmin [ns] Module Density per Rank tAS, tCS [ns] tAH, TCH [ns] tDS [ns] tDH [ns] not used tRCmin [ns] tRFCmin [ns] tCKmax [ns] tDQSQmax [ns] tQHSmax [ns] not used DIMM PCB Height not used SPD Revision Checksum of Byte 0-62 JEDEC ID Code of Infineon (1) JEDEC ID Code of Infineon (2 - 8) Module Manufacturer Location Part Number, Char 1 Part Number, Char 2 Part Number, Char 3
Data Sheet
28
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
SPD Contents Table 14 SPD Codes for HYS72D[128/64/32][300/320]GBR-6-C HYS72D128320GBR-6-C HYS72D64300GBR-6-C HYS72D64320GBR-6-C HYS72D32300GBR-6-C 256 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 33 32 33 30 30 47 42 52 36 43 20 20 20 20 20 xx xx xx xx xx FF Rev. 1.0, 2004-03 07302003-2MI6-FOP1
Product Type & Organization
1 GByte x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 31 32 38 33 32 30 47 42 52 36 43 20 20 20 20 xx xx xx xx xx FF
512 MB x72 1 Rank PC2700R- 25330 Rev 0.0 HEX 36 34 33 30 30 47 42 52 36 43 20 20 20 20 20 xx xx xx xx xx FF
512 MB x72 2 Ranks PC2700R- 25330 Rev 0.0 HEX 36 34 33 32 30 47 42 52 36 43 20 20 20 20 20 xx xx xx xx xx FF0
Label Code Jedec SPD Revision Byte# 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 - 98 99 -127 Description Part Number, Char 4 Part Number, Char 5 Part Number, Char 6 Part Number, Char 7 Part Number, Char 8 Part Number, Char 9 Part Number, Char 10 Part Number, Char 11 Part Number, Char 12 Part Number, Char 13 Part Number, Char 14 Part Number, Char 15 Part Number, Char 16 Part Number, Char 17 Part Number, Char 18 Module Revision Code Test Program Revision Code Module Manufacturing Date Year Module Manufacturing Date Week Module Serial Number (1 - 4) Blank
Data Sheet
29
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Package Outlines
6
0.1 A B C
Package Outlines
133.35 128.95 2.64 MAX. A
4 0.1 28.58 0.13
0.15 A B C
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
B 0.4
C
1.27 0.1 49.53
64.77 95 x 1.27 = 120.65
3.8 0.13
1.8 0.1 93
0.1 A B C 184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 6 Package Outlines - Raw Card A HYS72D32300GBR-[5/6]-C (1 Rank x 8)
L-DIMM-184-021
Data Sheet
30
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
A
4 0.1 28.58 0.13
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
BC 0.4 1.27 0.1
64.77 95 x 1.27 = 120.65
49.53
3.8 0.13
1.8 0.1 93
0.1 A B C 184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
L-DIMM-184-22-2 Figure 7 Package Outlines - Raw Card C HYS72D64300GBR-[5/6]-C (1 Rank x 4)
Data Sheet
31
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
A
4 0.1
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
28.58 0.13
BC 0.4 1.27 0.1 49.53 95 x 1.27 = 120.65 64.77 1.8 0.1 93 0.1 A B C 184
3.8 0.13
10
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
Burr max. 0.4 allowed
Figure 8 Package Outlines - Raw Card B HYS72D64320GBR-[5/6]-C (2 Ranks x8)
L-DIMM-184-23
Data Sheet
32
Rev. 1.0, 2004-03
17.8
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Package Outlines
0.1 A B C
133.35 128.95
0.15 A B C 4 MAX.
A
4 0.1 30.48 0.13
1 2.5 0.1
o0.1 A B C
6.62 2.175 6.35
92
BC 0.4 1.27 0.1
64.77 95 x 1.27 = 120.65
49.53
3.8 0.13
1.8 0.1 93
0.1 A B C
184
10 17.8
3 MIN.
Detail of contacts
0.2
1.27
1 0.05
2.5 0.2
0.1 A B C
L-DIMM-184-24-3
Burr max. 0.4 allowed
Figure 9 Package Outlines - Raw Card D HYS72D128320GBR-[5/6]-C (2 Ranks x4)
Data Sheet
33
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Application Note
7
Application Note
Power Up and Power Management on DDR Registered DIMMs (according to JEDEC ballot JC-42.5 Item 1173) 184-pin Double Data Rate (DDR) Registered DIMMs include two new features to facilitate controlled power-up and to minimize power consumption during low power mode. One feature is externally controlled via a systemgenerated RESET signal; the second is based on module detection of the input clocks. These enhancements permit the modules to power up with SDRAM outputs in a High-Z state (eliminating risk of high current dissipations and/or dotted I/Os), and result in the powering-down of module support devices (registers and Phase-Locked Loop) when the memory is in Self-Refresh mode. The new RESET pin controls power dissipation on the module's registers and ensures that CKE and other SDRAM inputs are maintained at a valid `low' level during power-up and self refresh. When RESET is at a low level, all the register outputs are forced to a low level, and all differential register input receivers are powered down, resulting in very low register power consumption. The RESET pin, located on DIMM tab #10, is driven from the system as an asynchronous signal according to the attached details. Using this function also permits the system and DIMM clocks to be stopped during memory Self Refresh operation, while ensuring that the SDRAMs stay in Self Refresh mode. Table 15 RESET Truth Table Register Inputs RESET H H H H L CK Rising Rising L or H High Z X or Hi-Z CK Falling Falling L or H High Z X or Hi-Z Data in (D) H L X X X or Hi-Z Register Outputs Data out (Q) H L Qo Illegal input conditions L
X: Don't care, Hi-Z: High Impedance, Qo: Data latched at the previous of CK rising and CK falling As described in the table above, a low on the RESET input ensures that the Clock Enable (CKE) signal(s) are maintained low at the SDRAM pins (CKE being one of the 'Q' signals at the register output). Holding CKE low maintains a high impedance state on the SDRAM DQ, DQS and DM outputs -- where they will remain until activated by a valid `read' cycle. CKE low also maintains SDRAMs in Self Refresh mode when applicable. The DDR PLL devices automatically detect clock activity above 20MHz. When an input clock frequency of 20MHz or greater is detected, the PLL begins operation and initiates clock frequency lock (the minimum operating frequency at which all specifications will be met is 95MHz). If the clock input frequency drops below 20MHz (actual detect frequency will vary by vendor), the PLL VCO (Voltage Controlled Oscillator) is stopped, outputs are made High-Z, and the differential inputs are powered down -- resulting in a total PLL current consumption of less than 1mA. Use of this low power PLL function makes the use of the PLL RESET (or G pin) unnecessary, and it is tied inactive on the DIMM. This application note describes the required and optional system sequences associated with the DDR Registered DIMM 'RESET' function. It is important to note that all references to CKE refer to both CKE0 and CKE1 for a 2bank DIMM. Because RESET applies to all DIMM register devices, it is therefore not possible to uniquely control CKE to one physical DIMM bank through the use of the RESET pin.
Data Sheet
34
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Application Note Power-Up Sequence with RESET -- Required 1. The system sets RESET at a valid low level. This is the preferred default state during power-up. This input condition forces all register outputs to a low state independent of the condition on the register inputs (data and clock), ensuring that CKE is at a stable low-level at the DDR SDRAMs. 2. The power supplies should be initialized according to the JEDEC-approved initialization sequence for DDR SDRAMs. 3. Stabilization of Clocks to the SDRAM The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches 20 MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. When a stable clock is present at the SDRAM input (driven from the PLL), the DDR SDRAM requires 200 sec prior to SDRAM operation. 4. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC initialization sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 5. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required (during this period, register inputs must remain stable). 6. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows their clock receivers, data input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in step 5. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 7. The system can begin the JEDEC-defined DDR SDRAM power-up sequence (according to the JEDECpproved initialization sequence). Self Refresh Entry (RESET low, clocks powered off) -- Optional Self Refresh can be used to retain data in DDR SDRAM DIMMs even if the rest of the system is powered down and the clocks are off. This mode allows the DDR SDRAMs on the DIMM to retain data without external clocking. Self Refresh mode is an ideal time to utilize the RESET pin, as this can reduce register power consumption (RESET low deactivates register CK and CK, data input receivers, and data output drivers). 1. 1. The system applies Self Refresh entry command. (CKELow, CSLow, RAS Low, CAS Low, WE High) Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares-- with the exception of CKE. 2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the registerm inputs (data and clock), and ensures that CKE, and all other control and address signals, are a stable low-level at the DDR SDRAMs. Since the RESET signal is asynchronous, setting the RESET timing in relation to a specific clock edge is not required. 3. The system turns off clock inputs to the DIMM. (Optional) a. In order to reduce DIMM PLL current, the clock inputs to the DIMM are turned off, resulting in High-Z clock
Data Sheet
35
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Application Note inputs to both the SDRAMs and the registers. This must be done after the RESET deactivate time of the register (t (INACT). The deactivate time defines the time in which the clocks and the control and address signals must maintain valid levels after RESET low has been applied and is specified in the register and DIMM documentation. b.The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register. The deactivate time defines the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during this operation. 4. The DIMM is in lowest power Self Refresh mode. Self Refresh Exit (RESET low, clocks powered off) -- Optional 1. Stabilization of Clocks to the SDRAM. The system must drive clocks to the application frequency (PLL operation is not assured until the input clock reaches ~20MHz). Stability of clocks at the SDRAMs will be affected by all applicable system clock devices, and time must be allotted to permit all clock devices to settle. Once a stable clock is received at the DIMM PLL, the required PLL stabilization time (assuming power to the DIMM is stable) is 100 microseconds. 2. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the JEDEC Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs, to be consistent with the state of the register outputs. 3. The system switches RESET to a logic `high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, RESET timing relationship to a specific clock edge is not required (during this period, register inputs must remain stable). 4. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 2. It is also a functional requirement that the registers maintain a low state at the CKE outputs to guarantee that the DDR SDRAMs continue to receive a low level on CKE. Register activation time (t (ACT) ), from asynchronous switching of RESET from low to high until the registers are stable and ready to accept an input signal, is specified in the register and DIMM do-umentation. 5. System can begin the JEDEC-defined DDR SDRAM Self Refresh Exit Procedure. Self Refresh Entry (RESET low, clocks running) -- Optional Although keeping the clocks running increases power consumption from the on-DIMM PLL during self refresh, this is an alternate operating mode for these DIMMs. 1. 1. System enters Self Refresh entry command. (CKE Low, CS Low, RAS Low, CAS Low, WE High) Note: Note: The commands reach the DDR SDRAM one clock later due to the additional register pipelining on a Registered DIMM. After this command is issued to the SDRAM, all of the address and control and clock input conditions to the SDRAM are Don't Cares -- with the exception of CKE. 2. The system sets RESET at a valid low level. This input condition forces all register outputs to a low state, independent of the condition on the data and clock register inputs, and ensures that CKE is a stable low-level at the DDR SDRAMs. 3. The system may release DIMM address and control inputs to High-Z. This can be done after the RESET deactivate time of the register (t (INACT) ). The deactivate time describes the time in which the clocks and the control and the address signals must maintain valid levels after RESET low has been applied. It is highly recommended that CKE continue to remain low during the operation. 4. The DIMM is in a low power, Self Refresh mode.
Data Sheet
36
Rev. 1.0, 2004-03
HYS72D[128/64/32][300/320]GBR-[5/6]-C Registered Double Data Rate SDRAM
Application Note Self Refresh Exit (RESET low, clocks running) -- Optional 1. The system applies valid logic levels to the data inputs of the register (address and controls at the DIMM connector). CKE must be maintained low and all other inputs should be driven to a known state. In general these commands can be determined by the system designer. One option is to apply an SDRAM `NOP' command (with CKE low), as this is the first command defined by the Self Refresh Exit sequence (ideally this would be a `NOP Deselect' command). A second option is to apply low levels on all of the register inputs to be consistent with the state of the register outputs. 2. The system switches RESET to a logic 'high' level. The SDRAM is now functional and prepared to receive commands. Since the RESET signal is asynchronous, it does not need to be tied to a particular clock edge (during this period, register inputs must continue to remain stable). 3. The system must maintain stable register inputs until normal register operation is attained. The registers have an activation time that allows the clock receivers, input receivers, and output drivers sufficient time to be turned on and become stable. During this time the system must maintain the valid logic levels described in Step 1. It is also a functional requirement that the registers maintain a low state at the CKE outputs in order to guarantee that the DDR SDRAMs continue to receive a low level on CKE. This activation time, from asynchronous switching of RESET from low to high, until the registers are stable and ready to accept an input signal, is t (ACT ) as specified in the register and DIMM documentation. 4. The system can begin JEDEC defined DDR SDRAM Self Refresh Exit Procedure. Self Refresh Entry/Exit (RESET high, clocks running) -- Optional As this sequence does not involve the use of the RESET function, the JEDEC standard SDRAM specification explains in detail the method for entering and exiting Self Refresh for this case. Self Refresh Entry (RESET high, clocks powered off) -- Not Permissible In order to maintain a valid low level on the register output, it is required that either the clocks be running and the system drive a low level on CKE, or the clocks are powered off and RESET is asserted low according to the sequence defined in this application note. In the case where RESET remains high and the clocks are powered off, the PLL drives a High-Z clock input into the register clock input. Without the low level on RESET an unknown DIMM state will result.
Data Sheet
37
Rev. 1.0, 2004-03
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Price & Availability of HYS72D32300GBR-6-C

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